This invention relates to semiconductor memory devices.
More particularly, the present invention relates to improved methods of fabricating semiconductor random access memory devices that utilize a magnetic field.
A magnetoresistive random access memory (hereinafter referred to as xe2x80x9cMRAMxe2x80x9d) device has a structure which includes ferromagnetic layers separated by a non-ferromagnetic layer. Information is stored as directions of magnetization vectors in magnetic layers. Magnetic vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions as information which are called xe2x80x9cParallelxe2x80x9d and xe2x80x9cAnti-parallelxe2x80x9d states, respectively. In response to Parallel and Anti-parallel states, the magnetic memory element represents two different resistances. The resistance indicates minimum and maximum values when the magnetization vectors of two magnetic layers point in substantially the same and opposite directions, respectively. Accordingly, a detection of changes in resistance allows an MRAM device to provide information stored in the magnetic memory element.
A MRAM device integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators, for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are fabricated in the process of complimentary metal oxide semiconductor (hereinafter referred to as xe2x80x9cCMOSxe2x80x9d) technology in order to lower the power consumption of the MRAM device. The CMOS process requires high temperature steps which exceeds 300xc2x0 C. for depositing dielectric and metal layers and annealing implants, for example.
Magnetic layers employ ferromagnetic materials such as cobalt-iron (Coxe2x80x94Fe) and nickel-iron-cobalt (NiFeCo) which require processing below 300xc2x0 C. in order to prevent intermixing of magnetic materials caused by high temperatures. Accordingly, magnetic memory elements need to be fabricated at a different stage after CMOS processing.
Further, magnetic memory elements contain components that are easily oxidized and also sensitive to corrosion. To protect magnetic memory elements from degradation and keep the performance and reliability of the MRAM device, a passivation layer is formed over magnetic memory elements.
In addition, the performance of the magnetic memory element is sensitive to the surface conditions on which magnetic layers are deposited. A magnetic memory element includes very thin layers, some of which are tens of angstroms thick, which can lead to shorting through the tunneling junction. Accordingly, it is necessary to make a flat surface to prevent the characteristics of the MRAM device from degrading. Also, magnetic memory elements are typically very small which makes it extremely difficult to connect the magnetic memory element to circuitry by using photolithography processes where the alignment tolerances are tight. Further, the materials comprising the ferromagnetic layers are difficult to etch because they are typically non-volatile in conventional low temperature plasmas and are very thin which makes them sensitive to corrosion from conventional chlorine based chemistries.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
To achieve the objects and advantages specified above and others, an improved method of fabricating a MRAM device is disclosed. The method involves providing a substrate with a surface, forming a dielectric region with a surface positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench with a top width and a bottom width within the dielectric region, the trench including a first wherein an edge profile is formed.
A tapered MRAM device is deposited within the trench and positioned on the substrate wherein the tapered MRAM device has a surface. The MRAM device includes a first ferromagnetic region with a width and a thickness positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width and a thickness positioned on the non-ferromagnetic spacer layer, wherein a gap exists between the tapered MRAM device and the side of the trench.
In the preferred embodiment, the first ferromagnetic region includes a pinned synthetic anti-ferromagnetic region and the second ferromagnetic region includes a free ferromagnetic region. Further, the non-ferromagnetic spacer layer forms a tunneling junction between the first ferromagnetic region and the second ferromagnetic region.
The tapered MRAM device is deposited wherein the taper is formed by making the width of the first ferromagnetic region substantially greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer substantially greater than the width of the second ferromagnetic region. This is accomplished by controlling the edge profile of the trench.
In the preferred embodiment, the edge profile on the side of the trench forms an undercut gap on the side of the trench wherein the bottom width of the trench is substantially greater than the top width. This feature causes the width of the trench to decrease as the MRAM device is deposited wherein the width of each subsequently deposited layer within the trench is formed with a shorter width than the previously deposited layer. Hence, the MRAM device is formed with a taper, which decreases the likelihood of a shorting current from flowing directly between the free and pinned ferromagnetic regions and, consequently, increases the device yield. Also, the presence of a shorting current can be minimized by surrounding the MRAM device with an oxide or by oxidizing a portion of the MRAM device. An advantage of this method is the elimination of etching steps that utilize corrosive elements, such as chlorine (Cl), which can damage the thin magnetic layers typically used in an MRAM device.